Crate memory_aarch64

This crate implements the virtual memory subsystem interfaces for Theseus on aarch64. memory uses this crate to get the memory layout and do other arch-specific operations on aarch64.

This is the top-level arch-specific memory crate. All arch-specific definitions for memory system are exported from this crate.

Re-exports

• pub use tlb_flush_by_theseus_asid as tlb_flush_all;

Macros

• asm_set_mmu_config_x2_x3
  Configures the MMU based on the pointer to a MmuConfig, in x2. This function makes use of x3 too. If the MMU was enabled on the origin core, it will be enabled by this on the target core.

Structs

• AggregatedSectionMemoryBounds
  The address bounds and flags of the initial kernel sections that need mapping.
• MmuConfig
  See read_mmu_config
• SectionMemoryBounds
  The address bounds and mapping flags of a section’s memory region.

Functions

• configure_translation_registers
  Configures paging for Theseus.
• disable_mmu
  Disable the MMU using aarch64 registers
• enable_mmu
  Enable the MMU using aarch64 registers
• find_section_memory_bounds
  Finds the addresses in memory of the main kernel sections, as specified by the given boot information.
• get_p4
  Returns the current top-level page table address.
• read_mmu_config
  Reads the current MMU configuration of the current CPU core, including the following system registers:
• set_as_active_page_table_root
  Sets the given page_table as active by updating the TTBR0 register.
• tlb_flush_by_theseus_asid
  Flushes all TLB entries with Theseus’ ASID (=0).
• tlb_flush_virt_addr
  Flushes the specific virtual address in TLB.