Struct pic::ChainedPics

pub struct ChainedPics { /* private fields */ }

A pair of chained PIC chips, which represents the standard x86 configuration.

Implementations

impl ChainedPics

pub fn init(master_mask: u8, slave_mask: u8) -> ChainedPics

Create a new interface for the standard PIC1 and PIC2 controllers, specifying the desired interrupt offsets. Then, it initializes the PICs in a standard chained fashion, which involved mapping the master PIC to 0x20 and the slave to 0x28 (standard rempaping), because even if we don’t use them (and disable them for APIC instead), we still need to remap them to avoid a spurious interrupt clashing with an exception.

pub fn mask_irqs(&self, master_mask: u8, slave_mask: u8)

Each mask is a bitwise mask for each IRQ line, with the master’s IRQ line 2 (0x4) affecting the entire slave IRQ mask. So if the master’s IRQ line 2 is masked (disabled), all slave IRQs (0x28 to 0x2F) are masked. If a bit is set to 1, it is masked (disabled). If set to 0, it is unmasked (enabled).

pub fn notify_end_of_interrupt(&self, interrupt_id: u8)

Figure out which (if any) PICs in our chain need to know about this interrupt. This is tricky, because all interrupts from pics[1] get chained through pics[0].

pub fn read_isr_irr(&self) -> IrqStatusRegisters

Reads the ISR and IRR registers of both the master and slave PIC.